1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to a highly-integrated dynamic random access memory having an array of rows and columns of memory cells each of which includes a capacitive element and a data transfer transistor.
2. Description of the Related Art
With the increasing needs for high performance and high reliability of digital computer systems, dynamic random access memories (DRAMs) are becoming more important in the role thereof. Typically, DRAMs include an array of memory cells each of which includes a capacitor and a metal oxide semiconductor (MOS) field effect transistor, which is connected between a bit line and the capacitor and has a gate electrode coupled to a corresponding one of word lines. The capacitor acts as a data storage element. The MOS transistor serves as a transfer gate for transferring data to or from the storage capacitor.
As the number of bits increases in order to provide higher packing density, the cell size decreases, the microfabrication of the storage capacitor and the transfer MOS transistor in each cell becomes significant. The storage capacitor decreases in the magnitude of storage capability to reduce the amount of signal charge carriers that can be stored in the capacitor at a time. The MOS transistor becomes thinner in its gate insulation film. These factors result in that, in addition to reduction of the signal voltage in magnitude, the internal electric field at the gate insulation film goes high in each cell under application of the same wordline voltage, thereby causing a resultant time-dependent dioxide breakdown (TDDB) to be extreme undesirably, which leads to decrease in the reliability of the DRAMs.